Memory access control device and method thereof

ABSTRACT

A memory access control device and method has a cache memory having a plurality of cache areas, each for storing image data of one macroblock, and a cache table having a plurality of table areas, corresponding to the plurality of cache areas, each for storing a validity flag indicating validity or an invalidity flag indicating invalidity of image data in a corresponding cache area and an in-frame address of image data of one macroblock stored in the corresponding cache area. A data request processor receives a data request including specification of an in-frame occupation region of requested image data from the image processor, determines target image data of at least one macroblock required to process the requested image data according to the in-frame occupation region of the requested image data, acquires the target image data from the cache memory, processes the requested image data using the acquired target image data, and outputs the processed image data to the image processor.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The present invention relates to a memory access control device, as wellas a method thereof, suitable for an image processor such as a movingimage decoder, which performs decoding of compressed data of a movingimage using an external memory.

2. Description of the Related Art

A moving image decoder, which performs decoding of compressed movingimage data such as Moving Picture Experts Group (MPEG) data, storesdecoded image data of a previous frame in a frame memory and performs adecoding process of a current frame while accessing the frame memory. Inthe case where encoded data such as encoded data of a predictive frame(P frame), which was encoded through an inter-frame prediction encodingprocess, is subjected to a decoding process, image data in a prior framewhich was referenced for encoding the P frame is needed for the decodingprocess. In this case, the decoding process of the encoded data of the Pframe is performed in units of macroblocks, each including apredetermined number of pixels, and image data in a reference frameincluding image data used for encoding a macroblock is needed to decodethe macroblock. Here, the same image data in the reference frame is usedfor the decoding process of the P frame a plurality of times throughoutthe entire decoding process. Thus, if image data of a reference frameused for the decoding process is read from the frame memory each time,the same image data is read from the frame memory a plurality of timesso that a large amount of image data is read from the frame memory perunit time.

The frame memory generally has a large capacity and a low read speed.Thus, when a large amount of image data is read from the frame memoryper unit time, all required image data may not be read in the worstcase. If the moving image decoder reads a large amount of image datafrom the external memory per unit time in a system in which the movingimage decoder shares the external memory with another module and somearea of the external memory are used as a frame memory, the speed atwhich another module reads data from the external memory is lowered,thereby reducing system performance.

In a variety of technologies suggested to overcome this problem (forexample, see Patent References 1 and 2), a cache memory is provided in amoving image decoder and image data read from an external memory for adecoding process is stored in the cache memory and, when the same imagedata as image data stored in the cache memory is needed for a decodingprocess, the same image data is not read from the external memory butquickly read from the cache memory.

PATENT REFERENCES

-   [Patent Reference 1] Japanese Patent Application Publication No.    2006-41898-   [Patent Reference 2] Japanese Patent Application Publication No.    2008-66913

To efficiently transmit image data, which is required by the movingimage decoder, from the external memory to the moving image decoderthrough cache control, there are performed a first process, in whichimage data which is not stored in the cache memory among the image datarequired by the moving image decoder is read from the external memoryand the read image data is then stored in the cache memory, and a secondprocess, in which the image data required by the moving image decoder isread from the cache memory and the read image data is then provided tothe moving image decoder. However, the first process and the secondprocess are not synchronized with each other and reading of the imagedata from the external memory in the first process is performed ascontinuously as possible.

However, it requires a certain time to send a read request to theexternal memory from the request of the moving image decoder and then tostore image data read from the external memory in the cache memory. Onthe other hand, when the moving image decoder performs a decodingprocess of a plurality of macroblocks of a P frame, there may be a needto reference the same image data twice or more to decode some of theplurality of macroblocks. Therefore, if the first and second processesare not synchronized, a request to read the same image data may beredundantly generated. Generation of such a redundant read requestwastes data communication bands between the external memory and thecache memory and also inhibits access of another module to the externalmemory, thereby reducing system efficiency.

Therefore, there remains a need for a memory access control device thatcan perform the first and second processes asynchronously withoutredundantly generating a read request of image data and can efficientlyprovide image data from the external memory to an image processor, suchas a moving image decoder. The present disclosure addresses this need.

SUMMARY OF THE INVENTION

One aspect of the present invention is a memory access control devicethat can read image data in units of macroblocks, into which one frameis divided, from an external memory storing image data of the one frame,then process image data requested by an image processor based on theread image data, and provide the processed image data to the imageprocessor as requested image data.

The memory access control device includes a cache memory having aplurality of cache areas, each capable of storing image data of onemacroblock and a cache controller having a cache table and a datarequest processor. The cache table can have a plurality of table areascorresponding to the plurality of cache areas. Each of the plurality oftable areas can store at least a validity flag indicating validity or aninvalidity flag indicating invalidity of image data in a correspondingcache area and an in-frame address of image data of one macroblockstored in the corresponding cache area.

The data request processor can receive a data request includingspecification of an in-frame occupation region of the requested imagedata from the image processor, determine target image data of at leastone macroblock required to process the requested image data according tothe in-frame occupation region of the requested image data, acquire thetarget image data from the cache memory, process the requested imagedata using the acquired target image data, and output the processedimage data to the image processor.

The data request processor can select, for each macroblock of the targetimage data, one table area in the cache table as an update table areawhen the table area does not store both the in-frame address of thetarget image data and the validity flag indicating validity, store thein-frame address of the target image data and the invalidity flag in theupdate table area, and output a read request instructing transmission ofthe target image data from the external memory to the cache memory.

The data request processor can store or set, when the image data of onemacroblock has been read from the external memory and stored in thecache memory, the validity flag of the respective table area storing thein-frame address of the read image data of the one macroblock.

The data request processor can acquire the target image data to processthe requested image data from the cache area corresponding to the tablearea that stores both the validity flag and the in-frame address of thetarget image data.

Each of the plurality of table areas also can store a scheduled accesscounter that counts the number of scheduled accesses to thecorresponding cache area.

The data request processor can increase the scheduled access counter by“1” in response to the data request, if the target image data is storedin the corresponding cache area and the read request for the targetimage data has not been output, or if the read request for the targetimage data has been output and the target image data has not been storedin the corresponding cache area.

The data request processor can decrease the scheduled access counter ifthe target image data read from the corresponding cache area has beenused to process the requested image data.

The data request processor can select the update table area when theupdate table area does not store both the in-frame address of the targetimage data and the validity flag, and the scheduled access counter ofthe updated table area does not have a value of “1” or more.

The data request processor can increase the scheduled access counter ofthe update table area by “1” and output the read request instructingtransmission of the target image data from the external memory to thecache memory.

The data request processor can acquire the target image data to processthe requested image data from the cache area corresponding to the tablearea that stores both the validity flag and the in-frame address of thetarget image data, and decrease the scheduled access counter of thetable area by “1”.

The image processor successively decodes image data for each frame andthe external memory stores image data of a previous frame decoded by theimage processor. The data request processor can receive the data requestfrom the image processor requesting image data of the previous framerequired to decode image data of a current frame, process the requestedimage data based on target image data read from the external memorythrough the cache memory, and output the processed image data to theimage processor.

The data request processor can include a Direct Memory Access (DMA)controller that implements DMA transmission of the image data betweenthe external memory module and the cache memory.

Another aspect of the present invention is a method of controllingmemory access for the memory access control device. The method, which isexecutable by the data request processor, comprising the steps of:receiving a data request including specification of an in-frameoccupation region of the requested image data from the image processor,determining target image data of at least one macroblock required toprocess the requested image data according to the in-frame occupationregion of the requested image data, acquiring the target image data fromthe corresponding cache area, and processing the requested image datausing the acquired target image data and outputting the processed imagedata to the image processor.

When any table area in the cache table does not store both the in-frameaddress of the target image data and the validity flag, the methodfurther comprises the steps of selecting, for each macroblock of thetarget image data, each table area in the cache table not storing boththe in-frame address of the target image data and the validity flag asan update table area, storing the in-frame address of the target imagedata and the invalidity flag in the update table area, and outputting aread request instructing transmission of the target image data from theexternal memory to the cache memory.

The storing step comprises storing the validity flag of the respectivetable area storing the in-frame address of the read image data of theone macroblock when the image data of one macroblock has been read fromthe external memory and stored in the cache memory.

The acquiring step acquires the target image data to process therequested image data from the cache area corresponding to the table areathat stores both the validity flag and the in-frame address of thetarget image data.

When the in-frame address of target image data and the validity flag areboth stored in the cache table, a request to read the target image datafrom the external memory is not output. Accordingly, it is possible toavoid generation of a redundant read request, thereby achievingefficient image data provision.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a configuration of a moving imagedecoding module including a memory access control device according to anembodiment of the invention.

FIG. 2 illustrates a compression encoding process of a P frame in acompression procedure for obtaining compressed data that is to bedecoded by a moving image decoder of the moving image decoding module.

FIG. 3 illustrates a method of specifying image data in the embodiment.

FIG. 4 is a block diagram illustrating a configuration of the memoryaccess control device.

FIG. 5 is a flowchart showing operation of the memory access controldevice.

DETAILED DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will now be described with reference to thedrawings.

FIG. 1 is a block diagram illustrating a configuration of a moving imagedecoding module 100 including a memory access control device 10according to an embodiment of the invention. The moving image decodingmodule 100 receives a command from a host CPU (not shown) through a bus101A, reads and decodes compressed image data and compressed alpha dataof a moving image from a ROM (not shown) connected to a bus 101B, andstores the decoded image data and alpha data of the moving image in anexternal memory module 102 including a Synchronous Dynamic Random AccessMemory (SDRAM) or the like connected to a bus 101C. In addition to themoving image decoding module 100, a different module such as a graphicsmodule is connected to the bus 101C. The moving image decoding module100 shares the external memory module 102 with the different module.

Bus interfaces (I/F) 21A, 21B, and 21C in the moving image decodingmodule 100 are interfaces which mediate data exchange through the buses101A, 101B, and 101C. A host interface 22 is an interface which receivesa command output by a device connected to the bus 101A through the businterface 21A, and stores the received command in an internal commandbuffer 22A and provides the command to each associated portion in themoving image decoding module 100. A register group 23 is a group ofregisters for storing control information for controlling each portionof the moving image decoding module 100 or storing data exchangedbetween each portion thereof. A ROM interface 24 includes thereinbuffers 24A and 24B, each of which is a First-In First-Out (FIFO)buffer. The ROM interface 24 receives compressed image data of a movingimage read from the ROM (not shown) connected to the bus 101B throughthe bus interface 21B and stores the compressed image data in the buffer24A and provides stored compressed image data to a moving image decoder25 in chronological order. The ROM interface 24 also receives compressedimage data of a moving image read from the ROM (not shown) connected tothe bus 101B through the bus interface 21B and stores the compressedimage data in the buffer 24B and provides stored compressed image datato an alpha data decoder 26 in chronological order.

The moving image decoder 25 is a device that performs a decoding processon compressed image data of a moving image according to a decodingprocess execution command received through the host interface 22. Here,control information, such as a storage start address in the ROM, of thecompressed image data that is to be decoded is stored in a predeterminedregister of the register group 23 through the host interface 22 beforethe decoding process is performed. Upon receiving the decoding processexecution command, the moving image decoder 25 reads compressed imagedata, which is to be decoded, from the ROM (not shown) with reference tothe control information in the predetermined register and performs adecoding process on the read compressed image data.

In this embodiment, the compressed image data to be decoded by themoving image decoder 25 is obtained through the following compressionprocess. First, independent frames (I frames) to be encoded are selectedfrom constituent frames of a moving image and remaining ones of theconstituent frames are selected as predictive frames (P frames) that areto be subjected to inter-frame predictive coding. Image data of each Iframe is divided into 16×16 pixel macroblocks and each macroblock isthen converted into compressed image data according to a predeterminedcompression algorithm. Similar to the I frame, image data of each Pframe is also divided into macroblocks of 16×16 pixels. Each P frame issubjected to an inter-frame predictive coding process involving motioncompensation to generate compressed image data.

More specifically, in the inter-frame predictive coding process, asillustrated in FIG. 2, a P frame or an I frame prior to the object Pframe to be encoded is selected as a reference frame. Then, for eachmacroblock MBx of the to-be-encoded P frame, a 16×16 pixel regionrepresenting an image most similar to an image of the object macroblockMBx is selected as a reference region MBx′ from among image data of theselected reference frame and the difference between image data of theobject macroblock MBx and image data of the reference region MBx′ isthen compressed. Although the reference region MBx′ covers fourmacroblocks MBa, MBb, MBc, and MBd of the reference frame in most casesas illustrated in FIG. 2, the reference region MBx′ may also rarelycover 3 or less macroblocks. The moving image decoder 25 receives anddecodes the compressed image data of the I and P frames obtained throughsuch a compression process.

Referring back to FIG. 1, the alpha data decoder 26 is a device thatperforms a decoding process on compressed alpha data of a moving imageaccording to a decoding process execution command received through thehost interface 22. Here, control information, such as a storage startaddress in the ROM, of the compressed alpha data that is to be decodedis stored in a predetermined register of the register group 23 throughthe host interface 22 before the decoding process is performed. Uponreceiving the decoding process execution command, the alpha data decoder26 reads compressed alpha data, which is to be decoded, from the ROM(not shown) with reference to the control information in thepredetermined register and performs a decoding process on the readcompressed alpha data.

The external memory interface 27 is an interface that mediates dataexchange through the external memory module 102 and each of the movingimage decoder 25 and the alpha data decoder 26. In this embodiment, aspecific storage region of the external memory module 102 is used as aframe buffer that stores image data decoded by the moving image decoder25. The external memory interface 27 includes a Direct Memory Access(DMA) controller (DMAC) that implements DMA transmission between theexternal memory module 102 and the cache memory 11 that is describedlater.

The following is a description of a P frame decoding process that isperformed using the external memory module 102 during the decodingprocess performed by the moving image decoder 25. The P frame decodingprocess is performed in units of 16×16 pixel macroblocks, similar to theI frame decoding process. However, the P frame is decoded with referenceto image data of a reference region in a reference frame.

The memory access control device 10 included in the moving imagedecoding module 100 includes a cache memory 11 and a cache controller 12as a means for providing image data of a reference region to the movingimage decoder 25 that performs the P frame decoding process.

When the moving image decoder 25 performs decoding on compressed data ofone macroblock of the P frame, the moving image decoder 25 transmits adata request, including specification of an address of a referenceregion in a reference frame required for the decoding, to the cachecontroller 12. In this embodiment, each pixel of a frame is specified byboth a pixel address X indicating the ordinal number of the pixel in thehorizontal direction and a pixel address Y indicating the ordinal numberof the pixel in the vertical direction.

The moving image decoder 25 uses block addresses having low resolutionrather than pixel addresses as addresses for specifying the referenceregion. Specifically, in this embodiment, the moving image decoder 25uses a block address XB obtained by removing the least significant bitof the pixel address X and a block address YB obtained by removing twoleast significant bits of the pixel address Y as addresses forspecifying the reference region. As shown in FIG. 3, the block addressesXB and YB are addresses indicating the horizontal and vertical positionsof a corresponding block when the pixels of a frame are divided intoblocks, each including 4 horizontal pixels and 2 vertical pixels. Inthis embodiment, to acquire image data of the reference region in the Pframe decoding process, the moving image decoder 25 outputs a datarequest to the cache controller 12, the data request including blockaddresses XB and YB of a left upper corner of the reference region, thenumber of blocks in a horizontal direction in the reference region, andthe number of blocks in a vertical direction of the reference region.

FIG. 4 is a block diagram illustrating a configuration of the cachecontroller 12 that constructs (i.e., processes) and provides image dataof a reference region to the moving image decoder 25 as requested imagedata according to such a data request. In FIG. 4, the cache memory 11 isalso shown for better understanding of the function of the cachecontroller 12.

In this embodiment, the cache memory 11 includes N (for example, 256)cache areas CA(k) (k=0 to N−1), each being capable of storing image dataof one macroblock. Image data of one macroblock read from the framebuffer region of the external memory module 102 is stored in each of thecache areas CA(k) (k=0 to N−1).

A data request processor 121 of the cache controller 12 generates anoutput task each time a data request is received from the moving imagedecoder 25. The output task is a task for acquiring, from the cachememory 11, image data of 1 to 4 macroblocks including a reference regionspecified by the data request and generating image data of the referenceregion from the acquired image data and outputting the generated imagedata to the moving image decoder 25. Execution of the output task ispaused when the image data of the 1 to 4 macroblocks including thereference region specified by the data request is not stored in thecache memory 11. Execution of an output task is also paused during aperiod in which a previous output task is outputting image data of areference region to the moving image decoder 25.

On the other hand, in order that the data request processor 121generates an output task, the data request processor 121 determinestarget image data required for the output task to generate image data ofa reference region, i.e., image data of 1 to 4 macroblocks covering thereference region. When one of the target image data is not stored in thecache memory 11, the data request processor 121 transmits a request toread the target image data to the external memory module 102 so that thetarget image data is transmitted from the external memory module 102 toone of the cache areas CA(k) (k=0 to N−1) of the cache memory 11. Thatis, when data stored in the cache memory 11 is missing some of thetarget data required by the output task, cache control is performed tocompensate for the missing data to enable execution of the output taskin this manner.

In this embodiment, a cache table 122 is provided in the cachecontroller 12 to allow the data request processor 121 to smoothlyperform such cache control. The cache table 122 contains N table areasTA(k) (k=0 to N−1) that are associated with the cache areas CA(k) (k=0to N−1) of the cache memory 11. Here, a scheduled access counter ACC(k),a valid flag VALID(k), and in-frame addresses XB(k) and YB(k) are storedin one table area TA(k). The in-frame addresses XB(k) and YB(k) areblock addresses XB and YB of a left upper corner of image data of amacroblock currently stored in the cache areas CA(k) or a left uppercorner of image data of a macroblock that is to be read from theexternal memory module 102 and then stored in the cache areas CA(k). Thevalid flag VALID(k) is a flag indicating whether or not image datastored in the cache area CA(k) is valid or invalid, and is “1” when thestored image data is valid and “0” when it is invalid. Stated otherwise,the valid flag indicates whether the image data is available or notavailable from the corresponding cache area. The scheduled accesscounter ACC(k) is a counter that counts the number of output tasks whichrequire target image data specified by the in-frame addresses XB(k) andYB(k), i.e., the number of scheduled accesses to the cache areas CA(k).

When the data request processor 121 generates each output task, the datarequest processor 121 monitors data stored in the cache memory 11 basedon the contents of the cache table 122 for each generated output task.When target image data required for the output task to generate imagedata of the reference region is stored in the cache memory 11, the datarequest processor 121 acquires the target image data from the cachememory 11. When the target image data required for the output task togenerate image data of the reference region is not stored in the cachememory 11, the data request processor 121 acquires the required targetimage data from the cache memory 11 after waiting until the target imagedata is stored in the cache memory 11. The data request processor 121then uses the acquired image data to construct the requested image dataof the reference region.

Details of cache control that the data request processor 121 performsusing the cache table 122 are described as follows. First, the datarequest processor 121 initializes the contents of the cache table 122each time an object frame of the moving image decoder 25 is switched.Specifically, the data request processor 121 sets all scheduled accesscounters ACC(k) (k=0 to N−1) to “0”, all valid flags VALID(k) (k=0 toN−1) to “0” indicating invalidity, and all in-frame addresses XB(k) (k=0to N−1) and YB(k) (k=0 to N−1) to “0”. Then, each time a data request isprovided from the moving image decoder 25, the data request processor121 generates an output task with image data of 1 to 4 macroblocksincluding a reference region specified by the data request, as targetimage data. The data request processor 121 performs the followingprocesses on each of the target image data.

<Process 1>

When there is a need to output a read request for the target image data,the data request processor 121 selects an update table area in the tableareas TA(k) (k=0 to N−1), updates the selected update table area, andoutputs read request of target image data. The following are details ofthis process.

First, the data request processor 121 determines whether or not thetarget image data is stored in the cache memory 11 and whether or not arequest to read the target image data has-been output. Specifically, thedata request processor 121 determines whether or not both the followingconditions are satisfied.

Condition a1-1: A table area TA(k), which stores both (1) blockaddresses XB and YB of a left upper corner of a macroblock to which thetarget image data belongs as in-frame addresses XB(k) and YB(k) and (2)a valid flag VALID(k) of “1”, is not present.

Condition a1-2: A table area TA(k), which stores both (1) blockaddresses XB and YB of a left upper corner of a macroblock to which thetarget image data belongs as in-frame addresses XB(k) and YB(k) and (2)a scheduled access counter ACC(k) having a value of “1” or more, is notpresent.

When both conditions a1-1 and a1-2 are satisfied, the data requestprocessor 121 selects an update table area from the table areas TA(k)(k=0 to N−1). Specifically, the data request processor 121 increments anindex k until a table area TA(k) whose scheduled access counter ACC(k)is “0” is found and determines, when such a table area TA(k) is found,that the table area TA(k) is an update table area. The data requestprocessor 121 determines image data of a cache area corresponding to theupdate table area is image data to be removed. The data requestprocessor 121 resets the index k to “0” after the index k reaches “N−1”.That is, the data request processor 121 sequentially and cyclicallyselects each of the table areas TA(k) (k=0 to N−1) as an update tablearea.

The data request processor 121 then stores block addresses XB and YB ofa left upper corner of the target image data as in-frame addresses XB(k)and YB(k) in the update table area TA(k) and also stores a valid flagVALID(k) of “0” indicating invalidity in the update table area TA(k) andincreases the value of the scheduled access counter ACC(k) by “1”.

The data request processor 121 then generates a read request whichincludes the in-frame addresses XB(k) and YB(k) of the target image dataand specifies a cache area CA(k) corresponding to the table area TA(k)as a destination of the target image data and then transmits thegenerated read request to the external memory module 102 through theexternal memory interface 27 and the bus interface 21C.

<Process 2>

The data request processor 121 increases a scheduled access counterACC(k) corresponding to the target image data by “1” when a request toread the target image data has been output to the external memory module102 although the target image data is not yet stored in the cache memory11. More specifically, when the table areas TA(k) (k=0 to N−1) include atable area TA(k), in which a scheduled access counter ACC(k) having avalue of “1” or more, a valid flag VALID(k) of “0” indicatinginvalidity, and the in-frame addresses XB(k) and YB(k) (k=0 to N−1) ofthe target image data are stored, the data request processor 121increases the scheduled access counter ACC(k) in the table area TA(k) by“1”.

<Process 3>

The data request processor 121 increases a scheduled access counterACC(k) corresponding to the target image data by “1” when the targetimage data is stored in the cache memory 11. More specifically, when thetable areas TA(k) (k=0 to N−1) include a table area TA(k), in which avalid flag VALID(k) having a value of “1” indicating validity and thein-frame addresses XB(k) and YB(k) (k=0 to N−1) of the target image dataare stored, the data request processor 121 increases the scheduledaccess counter ACC(k) in the table area TA(k) by “1”.

The data request processor 121 also performs the following processes.

<Process 4>

When image data of a macroblock is read from the external memory module102 according to the output read request and is then stored in a cachearea CA(k) specified in the read request, the data request processor 121stores or sets a valid flag VALID(k) of a table area TA(k) associatedwith the cache areas CA(k) (k) to “1” indicating validity.

<Process 5>

When an output task has read target image data from one cache area (forexample, the cache area CA(k1)) from among the cache areas CA(k) (k=0 toN−1) and then has used the read target image data to generate requestedimage data of a reference region, the data request processor 121decreases a scheduled access counter ACC(k1) of a table area TA(k1)corresponding to the cache areas CA(k1) by “1”.

Details of the processes performed by the data request processor 121 arefurther described below with reference to FIG. 5. The procedure of FIG.5 executes a flow from start to end each time a frame to be decoded isswitched. After start, Step S1 initializes contents of the cache table122. Specifically, the data request processor 121 sets all scheduledaccess counters ACC(k) (k=0 to N−1) to “0”, all valid flags VALID(k)(k=0 to N−1) to “0” indicating invalidity, and all in-frame addressesXB(k) (k=0 to N−1) and YB(k) (k=0 to N−1) to “0”.

Then, Step S2 monitors particular triggers T1, T2 and T3 occurring inthe data request processor 121. The trigger T1 is a data request fromthe moving image decoder 25. The trigger T2 is data read from theexternal memory module 102. The trigger T3 is an output task of data tothe moving image decoder 25.

When the trigger T1 occurs, the processes of Step S3 through Step S8 areexecuted. First, Step S3 determines whether target image data requestedfrom the moving image decoder 25 is present in the cache memory 11. Ifthe target image data is not present in the cache 11, the flow advancesto Step S4 to determine whether read request of the target image data tothe external memory module 102 is issued.

Namely, in Steps S3 and S4, the data request processor 121 determineswhether or not the target image data is stored in the cache memory 11and whether or not a request to read the target image data has beenoutput. Specifically, the data request processor 121 determines whetheror not both the following conditions are satisfied.

Condition a1-1: A table area TA(k), which stores both (1) blockaddresses XB and YB of a left upper corner of a macroblock to which thetarget image data belongs as in-frame addresses XB(k) and YB(k) and (2)a valid flag VALID(k) of “1”, is not present.

Conditional-2: A table area TA(k), which stores both (1) block addressesXB and YB of a left upper corner of a macroblock to which the targetimage data belongs as in-frame addresses XB(k) and YB(k) and (2) ascheduled access counter ACC(k) having a value of “1” or more, is notpresent.

When both conditions a1-1 and a1-2 are satisfied, the flow advances toStep S5 for carrying out the above mentioned process 5. Namely, the datarequest processor 121 selects an update table area from the table areasTA(k) (k=0 to N−1). Specifically, the data request processor 121increments an index k until a table area TA(k) whose scheduled accesscounter ACC(k) is “0” is found and determines, when such a table areaTA(k) is found, that the table area TA(k) is an update table area. Thedata request processor 121 determines image data of a cache areacorresponding to the update table area is image data to be removed. Thedata request processor 121 resets the index k to “0” after the index kreaches “N−1”. That is, the data request processor 121 sequentially andcyclically selects each of the table areas TA(k) (k=0 to N−1) as anupdate table area.

The data request processor 121 then stores block addresses XB and YB ofa left upper corner of the target image data as in-frame addresses XB(k)and YB(k) in the update table area TA(k) and also stores a valid flagVALID(k) of “0” indicating invalidity in the update table area TA(k) andincreases the value of the scheduled access counter ACC(k) by “1”.

The data request processor 121 then generates a read request whichincludes the in-frame addresses XB(k) and YB(k) of the target image dataand specifies a cache area CA(k) corresponding to the table area TA(k)as a destination of the target image data and then transmits thegenerated read request to the external memory module 102 through theexternal memory interface 27 and the bus interface 21C.

Thereafter, the flow advances to Step S6 to determine whether the dataprocesses of the current frame is completed. When the data processes ofone frame is not yet completed, the flow returns to Step S2 forcontinuously monitoring the particular triggers.

After the request of the target image data to the external memory module102 has been already outputted and before the target image datarequested from the moving image decoder 25 is not yet cached into thecache memory 11, another trigger T1 requesting the same target imagedata may occur. In such a case, the flow does not advance to Step S5,but branches to Step S7 so as to carry out the above mentioned process2. Namely, the data request processor 121 increases a scheduled accesscounter ACC(k) corresponding to the target image data by “1” when arequest to read the target image data has been output to the externalmemory module 102 although the target image data is not yet stored inthe cache memory 11. More specifically, when the table areas TA(k) (k=0to N−1) include a table area TA(k), in which a scheduled access counterACC(k) having a value of “1” or more, a valid flag VALID(k) of “0”indicating invalidity, and the in-frame addresses XB(k) and YB(k) (k=0to N−1) of the target image data are stored, the data request processor121 increases the scheduled access counter ACC(k) in the table areaTA(k) by “1”. Thereafter, the flow advances to Step S6 to determinewhether the data processes of the current frame is completed. When thedata processes of one frame is not yet completed, the flow returns toStep S2 for continuously monitoring the particular triggers.

Then, for example, a trigger T2 occurs in Step S2, and the flow advancesfrom Step S2 to Step S9 where the before mentioned process 4 isperformed. Namely, when image data of a macroblock is read from theexternal memory module 102 according to the output read request and isthen stored in a cache area CA(k) specified in the read request, thedata request processor 121 stores or sets a valid flag VALID(k) of atable area TA(k) associated with the cache areas CA(k) to “1” indicatingvalidity. Thereafter, the flow advances to Step S6 to determine whetherthe data processes of the current frame is completed. When the dataprocesses of one frame is not yet completed, the flow returns to Step S2for continuously monitoring the particular triggers.

Then, in case that a trigger T1 occurs for the image data already storedin the cache memory, the flow advances from Step S3 to Step S8 so as toperform the above mentioned process 3. Namely, the data requestprocessor 121 increases a scheduled access counter ACC(k) correspondingto the target image data by “1” when the target image data is stored inthe cache memory 11. More specifically, when the table areas TA(k) (k=0to N−1) include a table area TA(k), in which a valid flag VALID(k)having a value of “1” indicating validity and the in-frame addressesXB(k) and YB(k) (k=0 to N−1) of the target image data are stored, thedata request processor 121 increases the scheduled access counter ACC(k)in the table area TA(k) by “1”. Thereafter, the flow advances to Step S6to determine whether the data processes of the current frame iscompleted. When the data processes of one frame is not yet completed,the flow returns to Step S2 for continuously monitoring the particulartriggers.

Then, for example, a trigger T3 occurs, and the flow advances from StepS2 to Step S10 where the before mentioned process 5 is carried out.Namely, when an output task has read target image data from one cachearea (for example, the cache area CA(k1)) from among the cache areasCA(k) (k=0 to N−1) and then has used the read target image data togenerate requested image data of a reference region, the data requestprocessor 121 decreases a scheduled access counter ACC(k1) of a tablearea TA(k1) corresponding to the cache areas CA(k1) by “1”. By repeatingsuch output tasks, Step S6 finally determines that the processing of oneframe is completed, whereby the flow ends. Another flow of FIG. 5 iscommenced for a next frame.

In this embodiment, a request to read target image data is not outputwhen in-frame addresses XB(k) and YB(k) of the target image data and avalid flag VALID(k) indicating validity are stored in the cache table122. Accordingly, it is possible to avoid generation of a redundant readrequest, thereby realizing efficient image data provision. In addition,in this embodiment, even when a valid flag VALID(k) indicatinginvalidity of a target image data is stored in a table area TA(k) in thecache table 122, a request to read the target image data is not outputif a scheduled access counter ACC(k) of the table area TA(k) is “1” ormore. That is, a request to read the target image data is not outputwhen the target image data is being read from the external memory module102. Accordingly, it is possible to more reliably prevent redundant readrequests. Further, in this embodiment, when an output task, in whichimage data in a cache area CA(k) corresponding to a table area TA(k) isset as a target image data, is active and the value of a scheduledaccess counter ACC(k) indicating the number of scheduled accesses to thecache areas CA(k) is “1” or more, the table area TA(k) is not set as anupdate cache area and image data of a cache area CA(k) corresponding tothe table area TA(k) is not set as image data to be removed.Accordingly, it is possible to prevent removal of image data required byan active output task, to reduce the number of generations of a readrequest, and to prevent inhibition of access of another module to theexternal memory module 102, thereby increasing system efficiency.

Further, in this embodiment, since image data in the external memorymodule 102 are transmitted in units of macroblocks to the cache memory11, it is possible to increase the probability (i.e., cache hit rate)that, when the moving image decoder 25 has output a data request, targetimage data for acquiring image data requested by the data request isstored in the cache memory 11, and also to decrease the number of datatransmissions between the external memory module 102 and the cachememory 11, thereby increasing system efficiency.

Other Embodiments

Although the embodiment of the invention has been described above,various other embodiments are possible in the invention. The followingare examples.

(1) In the above embodiment, the memory access control device 10 is usedas a means for providing image data to the moving image decoder 25.However, the memory access control device 10 may also be used as a meansfor providing image data to a different type of image processor from themoving image decoder, for example, to a moving image encoder.

(2) There may be a need to read image data of a plurality of macroblocksas a result of the process 1 performed on a plurality of target imagedata while the image data of the plurality of macroblocks, which need tobe read, are also stored in areas of consecutive addresses in theexternal memory module 102 so that consecutive reading of the image datais possible. In this case, the data request processor 121 may beconfigured so as to instruct the external memory interface 27 to performDMA transmission of the image data of the plurality of macroblocks,which can be continuously read, from the external memory module 102 tothe cache memory 11. For example, let us assume that, when the movingimage decoder 25 performs decoding of the compressed image data of themacroblock MBx shown in FIG. 2, image data of the macroblocks MBc andMBd among the macroblocks MBa, MBb, MBc, and MBd which are target imagedata are not stored in the cache memory 11 and thus the image data ofthe macroblocks MBc and MBd need to be read from the external memorymodule 102. Here, when image data of the macroblock MBc and image dataof the macroblock MBd are stored in areas of consecutive addresses inthe external memory module 102, the data request processor 121 instructsthe external memory interface 27 to perform DMA transmission of theimage data of the macroblocks MBc and MBd. In this manner, it ispossible to further reduce the number of generations of a read requestand a DMA transmission, thereby increasing system efficiency.

1. A memory access control device connectable to an external memorystoring image data for processing image data requested by an imageprocessor, the memory access control device comprising: a cache memoryhaving a plurality of cache areas, each for storing image data of onemacroblock, wherein a plurality of predetermined number of macroblocksconstitute one frame; and a cache controller having a cache table and adata request processor, wherein the cache table has a plurality of tableareas, corresponding to the plurality of cache areas, each for storingat least a validity flag indicating validity or an invalidity flagindicating invalidity of image data in the corresponding cache area andan in-frame address of image data of one macroblock stored in thecorresponding cache area, wherein the data request processor isprogrammed to: receive a data request including specification of anin-frame occupation region of the requested image data from the imageprocessor; determine target image data of at least one macroblockrequired to process the requested image data according to the in-frameoccupation region of the requested image data; acquire the target imagedata from the corresponding cache area; and process the requested imagedata using the acquired target image data and output the processed imagedata to the image processor, wherein when any table area in the cachetable does not store both the in-frame address of the target image dataand the validity flag, the data request processor is programmed to:select, for each macroblock of the target image data, each table area inthe cache table not storing both the in-frame address of the targetimage data and the validity flag as an update table area; store thein-frame address of the target image data and the invalidity flag in theupdate table area; and output a read request instructing transmission ofthe target image data from the external memory to the cache memory,wherein, when image data of one macroblock has been read from theexternal memory and stored in the cache memory, the data requestprocessor is programmed to store the validity flag in the respectivetable area that stores, the in-frame address of the read image data ofthe one macroblock, and wherein the data request processor is programmedto acquire the target image data to process the requested image datafrom the cache area corresponding to the table area that stores both thevalidity flag and the in-frame address of the target image data.
 2. Thememory access control device according to claim 1, wherein: each of theplurality of table areas further stores a scheduled access counter thatcounts the number of scheduled accesses to the corresponding cache area,the data request processor is programmed to increase the scheduledaccess counter by “1” in response to the data request, if the targetimage data is stored in the corresponding cache area and the readrequest for the target image data has not been output, or if the readrequest for the target image data has been output and the target imagedata has not been stored in the corresponding cache area, and the datarequest processor is programmed to decrease the scheduled access counterif the target image data read from the corresponding cache area has beenused to process the requested image data.
 3. The memory access controldevice according to claim 1, wherein the data request processor includesa Direct Memory Access (DMA) controller that implements DMA transmissionof the image data between the external memory module and the cachememory.
 4. The memory access control device according to claim 1,wherein: the image processor successively decodes image data for eachframe and the external memory stores image data of a previous framedecoded by the image processor, and the data request processor isprogrammed to receive the data request from the image processorrequesting image data of the previous frame required to decode imagedata of a current frame, process the requested image data based ontarget image data read from the external memory through the cachememory, and output the processed image data to the image processor.
 5. Amemory access control device connectable to an external memory storingimage data for processing image data requested by an image processor,the memory access control device comprising: a cache memory having aplurality of cache areas, each for storing image data of one macroblock,wherein a plurality of predetermined number of macroblocks constituteone frame; and a cache controller having a cache table and a datarequest processor, wherein the cache table has a plurality of tableareas, corresponding to the plurality of cache areas, each for storing ascheduled access counter that counts the number of scheduled accesses toa corresponding cache area, a validity flag indicating validity or aninvalidity flag indicating invalidity of image data in the correspondingcache area, and an in-frame address of image data of one macroblockstored in the corresponding cache area, and wherein the data requestprocessor is programmed to: receive a data request includingspecification of an in-frame occupation region of the requested imagedata from the image processor; determine target image data of at leastone macroblock required to process the requested image data according tothe in-frame occupation region of the requested image data; acquire thetarget image data from the cache memory; process the requested imagedata using the acquired image data and output the processed image datato the image processor, wherein when any table area in the cache tabledoes not store both the in-frame address of the target image data andthe validity flag, and the scheduled access counter of the update tablearea does not have a value of “1” or more, the data request processor isprogrammed to: select, for each macroblock of the target image data,each table area in the cache table not storing both the in-frame addressof the target image data and the validity flag as an update table area;store the in-frame address of the target image data and the invalidityflag in the update table area; increase the scheduled access counter ofthe update table area by “1”, and output the read request instructingtransmission of the target image data from the external memory to thecache memory, wherein when image data of one macroblock has been readfrom the external memory and stored in the cache memory, the datarequest processor is programmed to store the validity flag in the tablearea that stores the in-frame address of the read image data of the onemacroblock, and wherein the data request processor is programmed toacquire the target image data to process the requested image data fromthe cache area corresponding to the table area that stores the validityflag and the in-frame address of the target image data, and decrease thescheduled access counter of the table area by “1”.
 6. The memory accesscontrol device according to claim 5, wherein the data request processorincludes a Direct Memory Access (DMA) controller that implements DMAtransmission of the image data between the external memory module andthe cache memory.
 7. The memory access control device according to claim5, wherein: the image processor successively decodes image data for eachframe and the external memory stores image data of a previous framedecoded by the image processor, and the data request processor isprogrammed to receive the data request from the image processorrequesting image data of the previous frame required to decode imagedata of a current frame, process the requested image data based on thetarget image data read from the external memory through the cachememory, and output the processed image data to the image processor.
 8. Amethod of controlling memory access for a memory access control devicethat is connectable to an external memory storing image data forprocessing image data requested by an image processor, the memory accesscontrol device having a cache memory having a plurality of cache areas,each for storing image data of one macroblock, wherein a plurality ofpredetermined number of macroblocks constitute one frame, and a cachecontroller having a cache table and a data request processor, whereinthe cache table has a plurality of table areas, corresponding to theplurality of cache areas, each for storing at least a validity flagindicating validity or an invalidity flag indicating invalidity of imagedata in the corresponding cache area, and an in-frame address of imagedata of one macroblock stored in the corresponding cache area, themethod, which is executable by the data request processor, comprisingthe steps of: receiving a data request including specification of anin-frame occupation region of the requested image data from the imageprocessor; determining target image data of at least one macroblockrequired to process the requested image data according to the in-frameoccupation region of the requested image data; acquiring the targetimage data from the corresponding cache area; and processing therequested image data using the acquired target image data and outputtingthe processed image data to the image processor, wherein when any tablearea in the cache table does not store both the in-frame address of thetarget image data and the validity flag, the method further comprisingthe steps of: selecting, for each macroblock of the target image data,each table area in the cache table not storing both the in-frame addressof the target image data and the validity flag as an update table area;storing the in-frame address of the target image data and the invalidityflag in the update table area; and outputting a read request instructingtransmission of the target image data from the external memory to thecache memory, wherein when the image data of one macroblock has beenread from the external memory and stored in the cache memory, storingthe validity flag of the respective table area storing the in-frameaddress of the read image data of the one macroblock, and wherein theacquiring step acquires the target image data to process the requestedimage data from the cache area corresponding to the table area thatstores both the validity flag and the in-frame address of the targetimage data.